This invention relates to phase switching synthesizers, and more specifically to a system for generating signal frequencies by employing a retimer circuit which provides glitch-free operation.
Many communication systems employ carrier frequencies in a GHz range. For example, HiPerLAN (High Performance Local Area Network) operates in the 5.2 GHz band (5.15 to 5.3 GHz) and consists of 5 channels spaced by 23.5294 MHz. One way to generate the carrier frequency is to use a phase-lock-loop frequency synthesizer, such as the one illustrated in FIG. 1.
FIG. 1 illustrates phase-lock-loop frequency synthesizer 70. A phase-lock-loop is an analog circuit that uses a negative feedback control loop to produce both an oscillator output frequency, which is synchronized with an input signal frequency, and an output voltage proportional to the input signal frequency changes. Specifically, FIG. 1 illustrates reference frequency 72 which is received at a first input terminal of phase detector 74. An output signal of phase detector 74 is received at an input terminal of voltage controlled oscillator (hereinafter referred to as xe2x80x9cVCOxe2x80x9d) 76 via loop filter 75. VCO 76 generates synthesized output signal 78. In addition, the signal generated by VCO 76 is looped back to a second input terminal of phase detector 74 via programmable divider 82. Programmable divider is configured to receive input frequency 80 and to generate signal 84 having a frequency equal to input frequency 80 divided by D, wherein D is an integer.
In one prior art embodiment, programmable divider unit 82 employs two divide-by-2 counters and a multiplexer to achieve a programmable frequency counter. However, the control of the multiplexer, as will be explained in greater detail below, can generate glitches that effect the operation of the synthesizer. One way to avoid such glitches is to employ slow rising control signals which control the operation of the multiplexer. However, this is not an effective method for avoiding glitches.
Thus, there is a need for a phase-shifting frequency dividing synthesizer which provides glitch-free operation.
The present invention, according to one embodiment, relates to a frequency divider system for generating a glitch-free output signal having a programmable frequency. The system comprises a frequency divider unit for receiving a signal having an input frequency, wherein the frequency divider unit is configured to generate a plurality of phase-shifted, retimer input signals. A retimer is coupled to the frequency divider unit and is configured to receive the retimer input signals, and to generate phase-shifted multiplexer input signals for receipt by a multiplexer. The retimer is further configured to receive retimer control signals and to generate corresponding multiplexer control signals. The multiplexer is coupled to the retimer and has input terminals configured to receive the conveyed plurality of phase-shifted, multiplexer input signals. The control terminals of the multiplexer are controlled by the multiplexer control signals so as to alternately and successively receive, at a time corresponding to the multiplexer control signal, the phase-shifted multiplexer input signals.
Thus, as the waveform of each said phase-shifted signal transitions between a xe2x80x9chighxe2x80x9d position and a xe2x80x9clowxe2x80x9d position, the multiplexer control signals are configured to be employed within a window period corresponding to the time when a phase-shifted signal experiences a transition. Glitches in the output frequency are avoided because the retimer is configured to change the input terminal of the multiplexer simultaneously with the xe2x80x9clowxe2x80x9d to xe2x80x9chighxe2x80x9d transition of the signal being switched to. According to another embodiment, glitches in the output frequency are avoided because the retimer is configured to change the input terminal of the multiplexer after the xe2x80x9clowxe2x80x9d to xe2x80x9chighxe2x80x9d transition of the signal being switched to, but prior to the xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d transition of the signal being switched from. Thus, the retimer is configured so that the signal received by the multiplexer changes from a first phase-shifted signal to a second phase-shifted signal only if the signal level of the first and second phase-shifted signals are in a xe2x80x9chighxe2x80x9d position.
In accordance with one embodiment of the present invention, the system employs two divide-by-two frequency divider units so as to divide the input frequency by four. Thus, the frequency divider unit generates four phase-shifted retimer input signals, such as signals having phases shifted by 0, 90 180 and 270 degrees. The system may also further comprise a counter for receiving the output signal generated by the multiplexer. The counter may comprise a divide-by-N counter, wherein N is input by a user, such that the divided frequency corresponds to the input frequency divided by 4N+K, wherein N and K are programmable.
The system may also comprise a pulse generator coupled to the divide-by-N counter. The pulse generator is configured to receive the states of the counter and to generate K pulses per output cycle. The K pulses are received by a four-state machine coupled to the pulse generator, which is configured to change state upon receipt of each of the K pulses. A decoder is coupled to the four-state machine and is configured to generate, based upon a state of the four-state machine, the retimer control signals for receipt by the retimer.